We briefly note that the entire privileged-level design described in this document could be replaced with an entirely different privileged-level design without changing the user-level ISA, and possibly without even changing the ABI. In particular, this privileged specification was designed to run existing popular operating systems, and so embodies the conventional level-based protection model. Alternate privileged specifications could embody other more flexible protection-domain models.
Do many/most other architectures have this attribute? The idea of replacing only one "side" of an architecture has never crossed my mind before and seems pretty cool.
To my knowledge, no other _widely deployed_ ISA has had this level of flexibility and foresight. In fact it's usually the opposite; the ISA is usually tightly coupled to the processor implementation that introduced it and the survival (= market success) of the immediate product is all that matters. However if it's successful, the successor(s) are now locked into support all the legacy of its predecessors.
I can only think of two other examples that successfully planned for the future: the IBM 360 (extremely CISC, but still alive today) and the DEC Alpha (beautiful design, but now mostly dead).
The Alpha disappeared because DEC went under and HP buried the CPU in favor of the Itanium, which is now also dead (mostly because of its technical shortcomings).
Not really, the Itanium VLIW architecture bet heavily on instruction-level parallellism as opposed to thread-level parallellism. In theory, the Itanium could issue and retire 3 instructions per cycle thereby making it competitive with x86 even on modest clock speeds.
The main problem was that not many programs could sustain 3 parallel instructions in their critical path, which meant that the compiler would often generate NOPs to fill the empty instruction slots. IIRC the Itanium typically achieved around 40% of its theoretical performance on conventional workloads. The term "NOP density" was coined specifically to research this problem.
There is another interesting observation in [1] that I haven't realized before: even if the compiler were to succesfully generate 3 instructions per cycle, the processor then had to possibly fetch 3 memory locations in that instruction cycle. If two of those were already in cache, the instruction would still stall on the third memory fetch. Contrast this with the implicit parallellism of hyperthreading, where the processor can continue executing a different thread when the current thread encounters a memory stall.
If Intel decided they would only produce Itaniums, without an AMD around to come up with the idea to create AMD64, we wouldn't have any option than to live with those shortcommings and eventually get improved designs.
This has come up so many times. It has far too little memory for Linux, but ignoring that, the MMU is broken and can't support virtual memory (not that they claim to support supervisor mode anywhere).
It is not designed as a general purpose microchip. It is designed as a microcontroller type microchip.
Memory is expansive, because Si chip area is expansive. The chip is designed for cheap special purpose applications. For that it fulfills the function.
Btw. you can run Linux on it, you just need to do something and can't simply put the latest and greatest Ubuntu distribution on it.
Careful - that's just the dev board without the M1 MCU itself. Taobao is pretty easy to access through the use of reshippers, I've used superbuy.com with much success but there are loads of options out there to pick up deals from Taobao and have them sent out of mainland China.
> I've used superbuy.com with much success but there are loads of options out there to pick up deals from Taobao and have them sent out of mainland China.
Please do tell more! I just made a Superbuy account but can't for the life of me figure out how to use it.
I'm somewhat fluent in Mandarin (my reading's a little rusty), so if that opens up additional options I'd love to know of them.
I had zero problems with Superbuy, copy the taobao or jd.com url to the top search bar and from there it should be trivial. Now, I do not have the taobao URL to show you but here's an interesting device (takes wide range DC via 5.5mm x 2.5mm plug and spits up two USB C and one USB A connection) https://item.jd.com/36832086035.html and via superbuy https://www.superbuy.com/en/page/buy?nTag=Home-search&from=s... add a cheap old 170W laptop charger from Lenovo with the right plug converter https://www.ebay.com/itm/282597814816 and presto, you have a super high wattage desktop USB charging station.
I want to see what Espressif, SiPeed, or some other vendor manages to do with RISC-V. I'm currently prototyping an A2DP vendor codec extension for Opus using an ESP32 board, and it is pretty painless. Bluetooth is the high value bit in my opinion.
Ah I’ve had really good experiences with SeeedStudio too, ordered plenty of things over the years - dangerous site for me to visit when I have money ;,)
That thing clocks a 400MHz out of the box and has coprocessors .. I'd also guess that risc-v isa is more performant than esp32's one (super wild guess). Let's say it sits in the middle :)
There are Fedora and FreeBSD builds for RISC-V. This particular item seems to have only 8MB though, so not really in (most people's) "computer" realm. ;)
RISC-V has a base ISA and many extensions, several of which are virtually required to run a "real" OS with features such as virtual memory. Every build of Linux I've seen for RISC-V is for an RVGC processor with an additional privileged mode.
Theoretically it should be possible to run "Linux" on a glorified microcontroller like the OP with μClinux, but I haven't seen that used for "real" work. It certainly couldn't be used as a general purpose OS.
In my opinion the line to draw is support for a privileged mode/protection rings/memory protection. Anything without that can run μClinux at best, which isn't much better than an RTOS. Without process isolation an operating system isn't very "general purpose."
I view wifi on these devices as an anti-feature. Too often, they rely on MVP web services with limited security, and require a full TCP/IP stack, alongside CA-based PKI (meaning, an inherently limited lifespan).
Not against a limited lifespan, but I really do like the model of a bridge device that communicates over wire or bluetooth, especially for consumer IOT - bt-based standards prevent vendor lock-in, for example.
What a joke of a "release" why are all such products almost immediately out of stock. Do they make 20 units? They don't even bother to say on their website when if ever they'll have more units available.
Imagine if you worked months to develop a product based on this chip and after all this work you can't use it because it is out of stock with no further info. This is why it'll make no sense to use such chips until they can be bought at digikey, mouser etc in serious quantities.
Sometimes it's a DSP or FPGA with blocks/instructions designed to implement common matrix transformations.
In this particular case a vendor on that site claims:
> 3. There are 5.9MB SRAM can be used for convolutional neural network acceleration, so, it is possible to run small model like tiny-yolo v2,MobileNet, as you see in face detection routine video.
This is super exciting. I hope the demand for these stimulates the copycat manufacturers into making even more RISC-V chips at lower and lower prices with better availability and options (aka, Arduino style).
RISC-V is an open ISA created by these guys: https://riscv.org/. ARM RISC chips are ARM IP and not open. There's a lot more to unpack there, but that's the gist of it.
As a dark pattern, the chip seems purpose-built for spying. It is interesting as we're witnessing the birth of a new category of embedded chips.
1. I wonder if a chip with these features will be standard in a couple of years, and somewhat shake up the embedded world.
2. ARM was said to be bet heavily on AI, but this chip seems to be ahead. Correct?
It is a chip that puts face-recognition (and sound-recognition) in a webcam almost for free, and it lowers the price of this capability dramatically. This lends itself to tracking people in public and commercial places, on a scale not yet seen. Maybe it even is the initial market? Regardless it represents an interesting new kind of device (which ARM was aiming for)!
We briefly note that the entire privileged-level design described in this document could be replaced with an entirely different privileged-level design without changing the user-level ISA, and possibly without even changing the ABI. In particular, this privileged specification was designed to run existing popular operating systems, and so embodies the conventional level-based protection model. Alternate privileged specifications could embody other more flexible protection-domain models.
Do many/most other architectures have this attribute? The idea of replacing only one "side" of an architecture has never crossed my mind before and seems pretty cool.
I can only think of two other examples that successfully planned for the future: the IBM 360 (extremely CISC, but still alive today) and the DEC Alpha (beautiful design, but now mostly dead).
If the choice had been Itanium or bust, it would have turned out much different outcome.
The main problem was that not many programs could sustain 3 parallel instructions in their critical path, which meant that the compiler would often generate NOPs to fill the empty instruction slots. IIRC the Itanium typically achieved around 40% of its theoretical performance on conventional workloads. The term "NOP density" was coined specifically to research this problem.
There is another interesting observation in [1] that I haven't realized before: even if the compiler were to succesfully generate 3 instructions per cycle, the processor then had to possibly fetch 3 memory locations in that instruction cycle. If two of those were already in cache, the instruction would still stall on the third memory fetch. Contrast this with the implicit parallellism of hyperthreading, where the processor can continue executing a different thread when the current thread encounters a memory stall.
[1] https://softwareengineering.stackexchange.com/questions/2793...
Complaining that it doesn't support Linux is like complaining that a Honda Civic can't compete in Formula One.
[0] https://github.com/kendryte/kendryte-freertos-sdk
It's the lack of full MMU that's the actual reason, it keeps the chip firmly in the microcontroller domain.
Memory is expansive, because Si chip area is expansive. The chip is designed for cheap special purpose applications. For that it fulfills the function.
Btw. you can run Linux on it, you just need to do something and can't simply put the latest and greatest Ubuntu distribution on it.
Please do tell more! I just made a Superbuy account but can't for the life of me figure out how to use it.
I'm somewhat fluent in Mandarin (my reading's a little rusty), so if that opens up additional options I'd love to know of them.
I want to see what Espressif, SiPeed, or some other vendor manages to do with RISC-V. I'm currently prototyping an A2DP vendor codec extension for Opus using an ESP32 board, and it is pretty painless. Bluetooth is the high value bit in my opinion.
https://www.seeedstudio.com/Sipeed-MAIX-I-module-w-o-WiFi-1s...
There's also a dev board, which is probably much more useful than these bare modules. Unfortunately also out of stock: https://www.seeedstudio.com/Sipeed-MAix-BiT-for-RISC-V-AI-Io...
Theoretically it should be possible to run "Linux" on a glorified microcontroller like the OP with μClinux, but I haven't seen that used for "real" work. It certainly couldn't be used as a general purpose OS.
Not against a limited lifespan, but I really do like the model of a bridge device that communicates over wire or bluetooth, especially for consumer IOT - bt-based standards prevent vendor lock-in, for example.
Imagine if you worked months to develop a product based on this chip and after all this work you can't use it because it is out of stock with no further info. This is why it'll make no sense to use such chips until they can be bought at digikey, mouser etc in serious quantities.
In this particular case a vendor on that site claims:
> 3. There are 5.9MB SRAM can be used for convolutional neural network acceleration, so, it is possible to run small model like tiny-yolo v2,MobileNet, as you see in face detection routine video.
https://github.com/kendryte/kendryte-doc-datasheet/blob/mast...